Verification Academy

UVM/OVM Verification

UVM Express

The UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation. If you don’t have a full-time verification expert on staff, or if you are not a full-time verification engineer, UVM Express might be for you. Most verification teams do not have a full-time verification expert on staff, have time and budget restrictions and cannot adopt the UVM in whole or adopt it as quickly as they might like. These teams are usually under-staffed, under-funded and over-worked. They are exactly the kind of people that the UVM is meant to help, but the first step towards adoption is too high.

Advanced UVM (Universal Verification Methodology)

The Advanced UVM (Universal Verification Methodology) module consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM Module to take your UVM understanding to the next level. You will learn how to build tests and verification environments, understand how to use the factory and configuration database to customize your verification IP, and how to create reusable stimulus sequences, including for multi-layer protocols.

Basic UVM (Universal Verification Methodology)

The Basic UVM (Universal Verification Methodology) module consists of 8 sessions with over 2 hours of instructional content. This module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The Verification Academy's goal for releasing the Basic UVM (Universal Verification Methodology) module is to raise the level of UVM (Universal Verification Methodology) knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.

Advanced OVM (&UVM - Universal Verification Methodology)

The Advanced OVM (& UVM) module's goal is to improve your understanding of OVM so you can move beyond basic block-level testbenches. Building on the concepts discussed in the Basic OVM module, you will learn how to assemble multi-level environments with layered stimulus sequences to handle more complex verification challenges. This module is primarily aimed at existing OVM engineers or managers who recognize that they need to take the next step in function verification and assumes a working knowledge of constrained-random verification and object-oriented programming.

Basic OVM (Open Verification Methodology)

The Basic OVM module consists of approximately 2.5 hours of content, and is divided into eight sessions. The module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained-random verification or object-oriented programming. Our goal for releasing the Basic OVM module is to raise your skill level to the point where you have sufficient confidence in your own technical understanding.

Dynamic Verification

Intelligent Testbench Automation (iTBA)

Achieving coverage closure is consistently identified as one of the most difficult challenges facing electronics product development teams. Over the past few years, the industry’s leading functional verification engineering teams have begun turning to a new and emerging technology called Intelligent Testbench Automation (iTBA). Intelligent Testbench Automation (iTBA) combines the high quality of directed testing with the high quantity of constrained random testing, and can be easily integrated into existing verification environments. This module provides a complete introduction to Intelligent Testbench Automation (iTBA), showing how you can achieve your coverage goals >10X faster, leaving you the option to reduce your verification time, expand your coverage targets even further, or both.

Evolving FPGA Verification Capabilities

Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone.

Static Verification

(ABV) Assertion-Based Verification

The design effort for complex ASICs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. One way to address increased design complexity is to supplement traditional functional verification methods with assertion-based verification (ABV).

(CDC) Clock-Domain Crossing Verification

For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SOC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis.

General Verification

Evolving Verification Capabilities

Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today's ASIC, FPGA and SoC design teams. Very few project managers would disagree with this statement. In fact, an often cited 2004 industry study by Collett International Research revealed that 35 percent of the total ASIC and FPGA development effort was spent in verification. In 2008, a Far West Research study (in conjunction with Mentor Graphics) indicated the verification effort has risen to 46 percent of the total ASIC and FPGA development effort.

Verification Planning and Management Introduction

The verification of any design of size is a daunting task that requires successful forethought in the form of formulating, architecting, strategizing and documenting an overall verification blueprint. The value of creating such a blueprint at the start of a project has been proven out through gathered metrics of successful projects. This verification planning and management (VPM) module is a 3 part, 90 min introduction towards creating such a verification blueprint.

Acceleration

Acceleration of SystemVerilog Testbenches with Co-Emulation

In this time of complex user electronics, system companies need dramatic improvements in verification productivity. Functional verification is known to be a huge bottleneck for today's designs, and it is often mentioned that it takes up 60-70% of a design cycle. It is no surprise then that companies are constantly looking for ways to enhance verification productivity. Often this is by looking at adopting advanced verification methodologies like OVM or UVM to enhance their verification effort.

Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation

SystemC continues to be used for virtual prototyping, one key values is performance. Performance that enables early validation of firmware in parallel with architecture. The release of the TLM2 standard enables many new technologies; co-emulation is a major beneficiary. As you move from an untimed high level architectural model to the more detailed RTL representation of your virtual prototype, performance drop-off is expected. With co-emulation you can regain the performance needed to do system level tasks as you did in your virtual prototype environment.