Acceleration
Acceleration are techniques that are used to address performance shortcomings of traditional simulation. For example, the design model (i.e., DUT) can be mapped into a hardware accelerator and run much faster during verification, while the testbench continues to run in simulation on a workstation. In this section of the Verification Academy, we focus on building verification acceleration skills.
Begin by viewing the two Acceleration Module session introductions:
- Introduction to H/W-Assisted Testbench Acceleration
- Introduction to Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
This session provides an introduction of hardware-assisted testbench acceleration.
This session provides an introduction of Virtual prototyping and why co-emulation is so attractive for SoC verification.
Course Modules include:
- Acceleration of SystemVerilog Testbenches with Co-Emulation
- Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
In this time of complex user electronics, system companies need dramatic improvements in verification productivity. Functional verification is known to be a huge bottleneck for today's designs, and it is often mentioned that it takes up 60-70% of a design cycle. It is no surprise then that companies are constantly looking for ways to enhance verification productivity. Often this is by looking at adopting advanced verification methodologies like OVM or UVM to enhance their verification effort.
SystemC continues to be used for virtual prototyping, one key values is performance. Performance that enables early validation of firmware in parallel with architecture. The release of the TLM2 standard enables many new technologies; co-emulation is a major beneficiary. As you move from an untimed high level architectural model to the more detailed RTL representation of your virtual prototype, performance drop-off is expected. With co-emulation you can regain the performance needed to do system level tasks as you did in your virtual prototype environment.