Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
SystemC continues to be used for virtual prototyping, one key values is performance. Performance that enables early validation of firmware in parallel with architecture. The release of the TLM2 standard enables many new technologies; co-emulation is a major beneficiary. As you move from an untimed high level architectural model to the more detailed RTL representation of your virtual prototype, performance drop-off is expected. With co-emulation you can regain the performance needed to do system level tasks as you did in your virtual prototype environment.
This module advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. SystemC simulation combined with co-emulation will deliver dramatic speedup of execution of verification. This module on Acceleration of SystemC and TLM-2.0 testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration.
The module “Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation” consists of approximately 1.5 hours of content, and is divided into six sessions of average 15 minutes each. The module is primarily aimed at existing SystemC H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating high level testbench environments. This module may also be of interest to S/W engineers who demand earlier access to systems for S/W development.
The target audience for this module is:
- Walk - content is of general interest, particularly to managers, but also engineers (first 3 sessions).
- Run - content is of interest to engineers interested in learning more implementation details and techniques (last 3 sessions).
Recommended Prerequisites:
- Evolving Verification Capabilities
- Acceleration of SystemVerilog Testbenches with Co-Emulation
- Verification Planning and Management Introduction
- Introduction to Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
- Why SystemC and TLM-2.0 Testbench Modeling?
- The SCE-MI 2.0 Standard
- The OSCI TLM-2.0 Standard
- Modeling SystemC TLM-2.0 Drivers and XLeratable Transactors
- Modeling SystemC TLM-2.0 Monitors and Talkers
This session provides an introduction of Virtual prototyping and why co-emulation is so attractive for SoC verification.
This session we will talk about the advantages of using SystemC and OSCI TLM-2.0 standard for testbench modeling. The high level of abstraction of SystemC in conjunction with TLM-2.0 makes it perfect for virtual prototyping with co-emulation. A case study will be used to illustrate the process of implementing an accelerated verification environment.
This session we will talk about the SCE-MI 2.0 standard in the context of how it can be used with emulation. In particular this session describes how SCE-MI is very compatible subset of SystemVerilog 1800 DPI standard, and why it is so relevant for co-emulation.
This session we will talk about the OSCI SystemC TLM-2.0 standard specifically in the context of how it can be used with emulation. Key areas include loosely-timed modeling, transport interfaces that are capable of transporting transactions and reusable transactions called generic payload.
This session we will talk in detail about how to model TLM-2.0 compliant drivers and acceleratable transactors. A case study will be used to show how to implement transactors for a Wishbone Bus protocol.
This session we will talk in detail about how to model TLM-2.0 compliant transactors. In this particular module we discuss the architecture of passive bus monitors and their associated acceleratable transactors. The Wishbone Bus protocol will be used to show how to implement monitor transactors.