Acceleration of SystemVerilog Testbenches with Co-Emulation
In this time of complex user electronics, system companies need dramatic improvements in verification productivity. Functional verification is known to be a huge bottleneck for today's designs, and it is often mentioned that it takes up 60-70% of a design cycle. It is no surprise then that companies are constantly looking for ways to enhance verification productivity. Often this is by looking at adopting advanced verification methodologies like OVM or UVM to enhance their verification effort. It makes verification engineers more productive, basically allowing them to faster develop reusable testbenches and automated tests. This module advocates that functional verification through modern testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. Simulation paired with co-emulation will deliver dramatic speedup of execution of verification.
This module on Acceleration of SystemVerilog Testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration. The module Acceleration of SystemVerilog Testbenches with Co-Emulation consists of approximately 1 hour of content, and is divided into four sessions. The module is primarily aimed at existing SystemVerilog H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating SystemVerilog testbench environments. This module may also be of interest to S/W engineers who demand earlier access to systems for S/W development.
The target audience for this module is:
- Walk - content is of general interest, particularly to managers, but also engineers.
- Introduction to H/W-Assisted Testbench Acceleration
- Testbench Acceleration Depicted
- Modeling for Acceleration
- Testbench Acceleration Flow
This session provides an introduction of hardware-assisted testbench acceleration.
This session provides a description of the considerations and recommended architecture utilized for acceleration of SystemVerilog testbenches with co-emulation. This includes a definition of how SystemVerilog testbench code (HVL) and design code (HDL) are partitioned.
This session introduces the basic requirements of a standards based co-emulation solution. It provides a technical description of the transaction-based communication mechanism between simulator and emulator.
This session provides the recommended flow for rapid bring up of an accelerated testbench environment that can be used for both pure simulation and for hardware-assisted acceleration of SystemVerilog testbenches.