Dynamic Verification
Dynamic verification is a process that involves generating input stimulus that is simulated, checking output responses, and then measuring coverage. In this section of the Verification Academy, we focus on building dynamic verification skills.
Course Modules include:
- Intelligent Testbench Automation (iTBA)
- Evolving FPGA Verification Capabilities
Achieving coverage closure is consistently identified as one of the most difficult challenges facing electronics product development teams. Over the past few years, the industry’s leading functional verification engineering teams have begun turning to a new and emerging technology called Intelligent Testbench Automation (iTBA). Intelligent Testbench Automation (iTBA) combines the high quality of directed testing with the high quantity of constrained random testing, and can be easily integrated into existing verification environments. This module provides a complete introduction to Intelligent Testbench Automation (iTBA), showing how you can achieve your coverage goals >10X faster, leaving you the option to reduce your verification time, expand your coverage targets even further, or both.
Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone.