Evolving FPGA Verification Capabilities
Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone. The change in FPGA capabilities has results in the emergence of advanced FPGA system-on-chip (SoC) solutions, which includes the integration of third-party IP, DSPs, and multiple microprocessors—all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address. This module introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
This Verification Academy module is intended to be highly interactive—allowing the attendee to ask detailed questions concerning developing a successful FPGA verification methodology.
The target audiences include:
- Crawl - content is technical, but at an introductory level, and of interest to novice engineers.
- Walk - content is of general interest, particularly to managers, but also engineers.
- Run - content is technical in nature, and of interest to engineers.
- Introduction from Harry Foster
- Overview and Welcome
- Code Coverage
- Test Planning
- Applied Assertions
- Transactions
- Self-Checking Testbenches
- Automatic Stimulus
- Functional Coverage
This session is a module introduction from Harry Foster and does not require a login to view.
This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
This session is an introduction to various code coverage metrics and how to apply them.
This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
This session shows you how to create a transaction level test bench using modules instead of object. You will quickly have a test bench where modules talk to each other using transactions instead of signals.
This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
This session introduces constrained-random stimulus for automatic stimulus generation.
This session shows you how to implement functional coverage using SystemVerilog covergroups.