General Verification
Course Modules include:
- Evolving Verification Capabilities
- Verification Planning and Management Introduction
Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today's ASIC, FPGA and SoC design teams. Very few project managers would disagree with this statement. In fact, an often cited 2004 industry study by Collett International Research revealed that 35 percent of the total ASIC and FPGA development effort was spent in verification. In 2008, a Far West Research study (in conjunction with Mentor Graphics) indicated the verification effort has risen to 46 percent of the total ASIC and FPGA development effort.
The verification of any design of size is a daunting task that requires successful forethought in the form of formulating, architecting, strategizing and documenting an overall verification blueprint. The value of creating such a blueprint at the start of a project has been proven out through gathered metrics of successful projects. This verification planning and management (VPM) module is a 3 part, 90 min introduction towards creating such a verification blueprint.