Static Verification
Static verification is the automatic analysis of a design model without the need to generate any input stimulus our check any output responses using simulation. In this section of the Verification Academy, we focus on building static verification skills.
Course Modules include:
- (ABV) Assertion-Based Verification
- (CDC) Clock-Domain Crossing Verification
The design effort for complex ASICs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. One way to address increased design complexity is to supplement traditional functional verification methods with assertion-based verification (ABV).
For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SOC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis.