Basic UVM (Universal Verification Methodology)
The Basic UVM (Universal Verification Methodology) module consists of 8 sessions with over 2 hours of instructional content. This module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The Verification Academy's goal for releasing the Basic UVM (Universal Verification Methodology) module is to raise the level of UVM (Universal Verification Methodology) knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.
This is not a substitute for hands-on language, methodology, or tool training.
A working knowledge of VHDL or Verilog is recommended for the majority of this course-module and prior knowledge of SystemVerilog would be useful, but not required.
The target audience for this module is:
- Walk - content is of general interest, particularly to managers, but also engineers.
- Introduction to UVM
- UVM "Hello World"
- Connecting Env to DUT
- Connecting Components
- Introducing Transactions
- Sequences and Tests
- Monitors and Subscribers
- Reporting
This session gives an overview of UVM, describes the motivation and benefits, and introduces some technical highlights.
This session walks through a short, simple example to get you started with UVM.
This session explains how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database.
This session explains the phases of a UVM component, focusing on how to use the build and connect phases to connect components together.
This session explains how to use transactions to communication between a sequencer and a driver in UVM.
This session explains how to create sequences of transactions, sequences of sequences, and how to start a sequence from a test.
This session explains how to create passive components such as monitors and subscribers, and how to connect them using analysis ports.
This session explains message reporting in UVM, and shows simple ways in which reporting can be customized.