The Universal Verification Methodology (UVM) is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
One of the most novel and exciting aspects of UVM is how it was developed. Rather than being developed by a single EDA vendor and rolled out as part of a marketing campaign, it was developed by a collection of industry experts representing microprocessor companies, networking companies, verification consultants, as well as EDA vendors. All the work was done under the auspices of Accellera. Under the umbrella of a standards organization, companies, even competitors, were able to come together in a collaborative environment to address the technical challenges of building a sophisticated verification methodology. The result is a powerful, multi-dimensional software layer and methodology for building verification environments. UVM is truly an industry initiative, one in which Mentor is proud to participate.
The Open Verification Methodology (OVM) is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on simulators from the Big-3 EDA companies.
Course Modules include:
- UVM Express
The UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation. If you don’t have a full-time verification expert on staff, or if you are not a full-time verification engineer, UVM Express might be for you. Most verification teams do not have a full-time verification expert on staff, have time and budget restrictions and cannot adopt the UVM in whole or adopt it as quickly as they might like. These teams are usually under-staffed, under-funded and over-worked. They are exactly the kind of people that the UVM is meant to help, but the first step towards adoption is too high.
- Advanced UVM (Universal Verification Methodology)
The Advanced UVM (Universal Verification Methodology) module consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM Module to take your UVM understanding to the next level. You will learn how to build tests and verification environments, understand how to use the factory and configuration database to customize your verification IP, and how to create reusable stimulus sequences, including for multi-layer protocols.
- Basic UVM (Universal Verification Methodology)
The Basic UVM (Universal Verification Methodology) module consists of 8 sessions with over 2 hours of instructional content. This module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The Verification Academy's goal for releasing the Basic UVM (Universal Verification Methodology) module is to raise the level of UVM (Universal Verification Methodology) knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.
- Advanced OVM (&UVM - Universal Verification Methodology)
The Advanced OVM (& UVM) module's goal is to improve your understanding of OVM so you can move beyond basic block-level testbenches. Building on the concepts discussed in the Basic OVM module, you will learn how to assemble multi-level environments with layered stimulus sequences to handle more complex verification challenges. This module is primarily aimed at existing OVM engineers or managers who recognize that they need to take the next step in function verification and assumes a working knowledge of constrained-random verification and object-oriented programming.
- Basic OVM (Open Verification Methodology)
The Basic OVM module consists of approximately 2.5 hours of content, and is divided into eight sessions. The module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained-random verification or object-oriented programming. Our goal for releasing the Basic OVM module is to raise your skill level to the point where you have sufficient confidence in your own technical understanding.
