Verification Academy Forum
Verification Methodology Discussion Forum
Formerly the OVM World Forum
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This forum is for topics related to UVM - Universal Verification Methodology.
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UVM:: new task basd phases:: excution order by mperyer 02/15/2012 - 2:31pm |
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This forum is for topics related to OVM - Open Verification Methodology.
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problem with ovm object utils by SMB 18 hours 44 min ago |
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This forum is for topics related to SystemVerilog and other Languages.
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can I use systemverilog feature " bind " to bind DUT internal signals? by aming 1 day 2 hours ago |
UVM/OVM Kit Downloads and User Contributions Forum
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Download any of the OVM Kits from 1.0 to 2.1.2 and the new UVM Kits from Accellera plus OVM and UVM User Contributed Downloads.
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Automate testbench-DUT connection code by avidan_efody 02/13/2012 - 5:01pm |
Announcements & Promotional Forum
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OVM/UVM updates and other notices of related interest including events and promotional activities from the community.
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See the Academy Trainers at DVCon 2012 by Administrator 02/14/2012 - 2:10pm |
What's Going On?
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