I am building a verification environment for a DUT that has multiple ports of the same type, for example ARINC 429. My company has multiple products with various numbers of A429 ports. The architecture will support upto 32 receivers and 32 transmitters. I am using the dual top model for the verification environment. So, I have a top_dut that instantiates the DUT and the protocol modules for each interface. I want to make this as reusable as possible. I am trying to use a generate block to instantiate multiple instances of the same protocol module like so
genvar i;
generate
for (i = 0; i < NUM_A429_RX; i++)
a429_rx_protocol_module #(unique string for interface name) a429_rx (port assignments);
endgenerate
This compiles in Questa, however it fails to load resulting in a bad handle or reference fatal error. When I use separate instantiations the simulation loads and runs. For the DUT I am verifying it isn't too bad because I only have two receive ports and one transmit port. But separate instantiations would be tedious for the design that we have that has 26 receive ports and 10 transmit ports.
Is using the generate statement allowed for this?