Hi everybody,
I have a question about SV modports. I'm using this simple example code:
interface example_if(); logic sig1; logic sig2; modport mod1(output sig1, input sig2); modport mod2(input sig1, output sig2); endinterface module module1(example_if.mod1 ex_if); initial begin ex_if.sig1 = 1; ex_if.sig2 = 1; end endmodule module top(); example_if ex_if(); module1 module1_inst(ex_if.mod1); endmodule
My guess was that by using the mod1 modport in the module, I would not be able to write to sig2, but when I simulate it, sig2 does become 1. How is this supposed to work? Am I making a mistake somewhere?
Thanks,
Tudor
It's not supposed to work, but unfortunately, the LRM is not explicitly clear enough to say that modport directions should be enforced.
Dave Rich
Mentor Graphics
http://go.mentor.com/drich
So basically it's just useful if you want to restrict access only to specific signals, but not their direction... Kind of useless.
I think that synthesis tools may enforce port directions. Unfortunately, too many simulator implementations have allowed this code to change the LRM to be stricter.
Dave Rich
Mentor Graphics
http://go.mentor.com/drich