Hai...
i want to generate a clk of frequency 10Mhz and want to check the frequency in checker or testcase .. wheather frequency is correct or not ,Can any help and teach me , how to do it in a better a way .
forever
#400 clk=~clk ;
Frequency checker in system verilog or verilog
February 8, 2012 - 7:07am
#1
Frequency checker in system verilog or verilog
Verification Guild http://bit.ly/zWkxBS
I did a google search on: VerificationGuild clock frequency assertion
There are many posts on this topic.
Ben Cohen
Do you think below works?
property name ( int clk_period);
@(posdege clk) disable iff (rst)
('1, current_time = $time) |=> (clk_period == ( $time - current_time) )
endproperty
// This is the correct way, you need the local variable current_time.
// You cannot do an assign from within the property.
// I move the clocking event to the assertion.
time clk_period = 20ns;
property p_period ( int clk_period);
time current_time;
disable iff (rst)
('1, current_time = $time) |=> (clk_period == ($time - current_time) );
endproperty : p_period
ap_period: assert property(@ (posedge clk) p_period(clk_period));
Ben Cohen SystemVerilog.us
Basic timing checks can be performed using Verilog timing checks like $period. You can put these into existing modules or interfaces, or bind them into your design.
Dave Rich
Mentor Graphics
http://go.mentor.com/drich