Write a bunch of assertions describing the "characteristics" of the FSM in say PSL/SVA and then provide RTL + properties to a formal verifier (model checker - MC). MC is the "mathematical engine" that you are looking for. Severak commerical MCs exist:
1 0-in from Mentor
2. IFV: from Cadence
3. Magellan from SNPS
4. Jaspergold from Jasper
5. Panda from SparkEDA
Write a bunch of assertions describing the "characteristics" of the FSM in say PSL/SVA and then provide RTL + properties to a formal verifier (model checker - MC). MC is the "mathematical engine" that you are looking for. Severak commerical MCs exist:
1 0-in from Mentor
2. IFV: from Cadence
3. Magellan from SNPS
4. Jaspergold from Jasper
5. Panda from SparkEDA
HTH
Ajeetha, CVC
www.cvcblr.com/blog
Ajeetha Kumari, CVC Pvt Ltd.
http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar