Hi,
I just completed course in Systemverilog with VMM and also completed two projects.
Basically i done many projects using VHDL verification, i try to convert one of the verification project from VHDL to SystemVerilog.
I am unable to understand requirement from the specification to put into verification using S.V language.
Here is the req: The com_tran signal shall tristate within 50ns when test_fpga_oe is
asserted low and test_en is asserted high.
And also how to verify some of the requirements which will have timing tolerances.
Could anyone please suggest me how to start this kind of requirement verification in S.V language.
regards,
Nivas.
This is something that basic Verilog timing checks can do. You don't normally see this in SystemVerilog books or examples because it it assumed you already know Verilog.
However, you can take advantage of the SystemVerilog bind construct to insert Verilog modules with timing checks into the design if you are not able to modify the RTL.
Dave Rich
Mentor Graphics
http://go.mentor.com/drich