I know that in VERA simulation, we can use +vera_random_seed=$(SEED) to change random seed without to re-compile. In fact i use shell script to get current time and pass it to vera seed. Every time I run simulaiton, the random data is not the same, it is very convenient.
I was wondering whether systemverilog has the same mechanics to change rand seed at command line.
Thanks!
Command line switches may be tool dependent.
In Questa, you can use the vsim switch -sv_seed [value]. You can also use random as value to generate unique seeds. It will print out the seed so you can replay it.
Dave Rich
Mentor Graphics
http://go.mentor.com/drich
Thanks! Dave!
Got it!