can I use systemverilog feature " bind " to bind DUT internal signals? | Verification Academy

Academy Home

Academy Login

The Verification Academy requires Javascript. Please enable Javascript in your browser or switch to a browser that supports Javascript in order to view this site.

can I use systemverilog feature " bind " to bind DUT internal signals?

2 posts / 0 new

Last post

February 21, 2012 - 3:50pm

#1

aming

Offline

Academy Total Access User

Joined: 11/13/2009

Posts: 19

can I use systemverilog feature " bind " to bind DUT internal signals?

Can anyone provide me an example to use systemverilog "bind" to verify the internal signals of a DUT?
thanks

February 23, 2012 - 10:56am

#2

dave_59

Offline

Verification Forum Moderator

Joined: 03/10/2010

Posts: 976

Re: can I use systemverilog feature " bind " to bind DUT internal signals?

This example will be used in my poster paper IP.3 The Testbench to DUT Connection at next week's DVCon

__________________

Dave Rich
Mentor Graphics
http://go.mentor.com/drich