Hi,
How can I create a Register Model with following specifications?
REG_A = {REG_1,......,REG_8}
- A register (Ex: REG_A) which is mapped to address offset 0x0020 is linked to 8 registers (REG_1 to REG_8).
- For Writing into those 8 registers I have to write sequential data 8 times in the REG_A & it will write all 8 registers REG_1 to REG_8 (kind of FIFO operations).
- Now, REG_1 to REG_8 Have different fields & access capability (for example REG_1 has all 32bits RW type, REG_2 has [4:0]: RW, others: RO).
So how to model this kind of DUT bahavior where the access to individual registers (REG_1 to REG_8) is not there. The only register accessible is REG_A from register sequence.
Can quirky registers be used to model this? Is there some better way than this?
Thanks,
Ashish