UVM register model/sequence layering question

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paulegan
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UVM register model/sequence layering question

I have a design with several blocks that use the same bus interfaces (AHB/APB) and I want to create a common environment that can be instantiated in the block environment for each block. We will be using the UVM 1.1. register model for the blocks, and the question I have is where to place the register model - in the common environment, or the block environment. The register model will be unique for each block, and the UVM register examples show the register sequencing layer connected only in the top level environment:

// Only set up register sequencer layering if the top level env
if(m_cfg.spi_rm.get_parent() == null) begin
m_cfg.spi_rm.APB_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);
end

I initially thought moving the register model to the block environment made sense (based on the above code). On the other hand, if we use the same class name for the register model, we can place the register model code in the common environment (note: makefile target would build unique register model specific to the block) and avoid the sin of duplicate code since the adapters, bus maps, and agents are the same for each block. Would the following code work:

// Only set up register sequencer layering if the top level env
if((m_cfg.spi_rm.get_parent() == null) || (m_cfg.spi_rm.get_parent() == <*common_block_identifier> ) begin
m_cfg.spi_rm.APB_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);
end