Academy News
Mentor Graphics Drives Broader Adoption of UVM
Press Release.
Mentor Graphics Corporation (NASDAQ: MENT) today announced expanded support for the Universal Verification Methodology (UVM). The UVM delivers productivity gains made possible by reuse in functional verification. For verification teams with minimal exposure to UVM, the first step to implement a UVM-based verification environment is simply getting started. To facilitate that first step, Mentor introduces UVM Express, a way to progressively adopt a UVM methodology. Other verification teams have an established UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved. For those verification teams, Mentor introduces UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog.
"Mentor continues to see massive interest in UVM, and we are committed to leading the effort to make UVM an integral part of every functional verification flow," said John Lenyo, vice president and general manager of the Design Verification Technology division at Mentor Graphics. "For verification teams using UVM for the first time, UVM Express makes getting started easy and intuitive, and extends rapid productivity gains to a broader scope of design projects. With UVM Connect, we've created a link between abstraction levels that enables design and verification engineers to take advantage of each level's best features without sacrificing the ability to reuse work."
Verification Horizons Blog
Knowledge Verification Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.
The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Latest blog post: Introducing UVM Connect by Tom Fitzpatrick
Additional blog posts include:
Verification Events at DVCon 2012
See the Academy Trainers at Booth #801
| February 27 - March 1, 2012 DoubleTree Hotel, San Jose, CA |
Improving SystemVerilog UVM Transaction Recording and Modeling
New article on the Design & Reuse website by Rich Edelman.
This article will introduce simple concepts such as transaction begin and transaction end, to more advanced concepts such as relationships, "tags", and other transaction attributes.
"The SystemVerilog UVM contains a transaction modeling abstraction, and has the ability to record this transaction model using a vendor specific API. This transaction model and vendor specific saved database is very powerful for debug, performance analysis and modeling for communication..."
UVM/OVM Recipe of the Month
Web Seminar Series featuring the UVM/OVM Online Cookbook
The UVM/OVM Online Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM and OVM.
This series of online seminars, will focus on a featured monthly "recipe" guiding users into a deeper understanding of the material.
Web seminar recipes include:
- Configuration in UVM - Archived
This session will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. You'll be shown how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. Then we'll cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
- More UVM Registers - Archived
This session will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.
- OVM to UVM Migration - Archived
A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.
- Sequence Layering - Archived
Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
- Intro to UVM Registers - Archived
The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM 2.1.2.
Learn from the contributing authors of the UVM/OVM Online Cookbook and register for all of the recipes.
*Seminar registration is fulfilled on Mentor.com
Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation Module
John Stickley - Subject Matter Expert.
A new addition to the Academy library is the second Acceleration Module. The Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation module authored by SME - John Stickley consists of approximately 1.5 hours of content, and is divided into six sessions of average 15 minutes each. The module is primarily aimed at existing SystemC H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating high level testbench environments. This module may also be of interest to S/W engineers who demand earlier access to systems for S/W development.
Sessions include:
- Introduction to Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
- Why SystemC and TLM-2.0 Testbench Modeling?
- The SCE-MI 2.0 Standard
- The OSCI TLM-2.0 Standard
- Modeling SystemC TLM-2.0 Drivers and XLeratable Transactors
- Modeling SystemC TLM-2.0 Monitors and Talkers
6 New Sessions added to the iTBA module
Mark Olen & Steve Chappell - Subject Matter Experts.
New additions to the Verification Academy Module library; 6 sessions of Intelligent Testbench Automation.
Sessions include:
- Integrating iTBA into an Existing Set of Directed Tests
- Integrating iTBA into an 'e' Environment
- Integrating iTBA into a SystemC Environment
- Distributed Simulation for Even Faster Functional Coverage
- Applications of Configurable Graphs
- Applications of Reactive Graphs
This session describes integrating Intelligent Testbench Automation into a directed test environment, re-using existing directed test code, and achieving >10X more functional coverage.
This session describes integrating Intelligent Testbench Automation into an 'e' environment, re-using existing eVCs, and achieving functional coverage >10X faster.
This session describes integrating Intelligent Testbench Automation into a SystemC environment, re-using existing SystemC VIP, and achieving functional coverage >10X faster.
This session describes how Intelligent Testbench Automation can distribute its process across a network of simulation servers, to achieve functional coverage goals even faster. iTBA realizes nearly linear results (i.e. 100 servers achieves better than 95X improvement), as overhead is less than 5%, and no redundant work is performed by each server. Automatic allocation of work, load balancing, and coverage monitoring will also be discussed.
This session describe show configurable graphs can be developed to support broad re-use and to allow stimulus to be easily focused on specific areas without modifying the graph source.
This session describes how graphs can be made dynamically reactive to opportunistically target coverage that depends on testbench or DUT state.
Verifying CDC Reconvergence with Silicon-Accurate Models with Questa CDC Web Seminar
Online
Multi-clock designs are subject to metastability causing mismatches between simulation and the silicon reality. This web seminar focuses on how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior.
Learn:
- How metastability can lead to functional issues in silicon.
- Why metastability cannot be verified by traditional simulation methods.
- The differences between current metastability modeling techniques.
Assertions Seminar - August 17th
Santa Clara, CA
Join Cliff Cummings from Sunburst Design as he presents a seminar covering assertions.
What you will learn:
- What assertions are.
- When and where to use assertions.
- See assertions examples that you use directly in your own designs.
Date, time and location:
- August 17, 2011
- 8:30 - 11:30 AM Pacific Time
- Santa Clara, Network Meeting Center at Techmart
Seating is limited and breakfast provided. Learn more and reserve your seat.
UVM/OVM Cookbook - Now Available
An encyclopedia of Verification Methodology!
Announced at DAC 2011, the UVM/OVM Online Methodology Cookbook is exclusively available at the Verification Academy.