A new addition to the Academy library is the second Acceleration Module. The Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation module authored by SME - John Stickley consists of approximately 1.5 hours of content, and is divided into six sessions of average 15 minutes each. The module is primarily aimed at existing SystemC H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating high level testbench environments. This module may also be of interest to S/W engineers who demand earlier access to systems for S/W development.

Sessions include:

• Introduction to Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation
• Why SystemC and TLM-2.0 Testbench Modeling?
• The SCE-MI 2.0 Standard
• The OSCI TLM-2.0 Standard
• Modeling SystemC TLM-2.0 Drivers and XLeratable Transactors
• Modeling SystemC TLM-2.0 Monitors and Talkers

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