Monday | February 27th | 8:30am - 5:00pm
UVM: Ready, Set, Deploy

This tutorial will be presented by expert verification methodology architects and engineers. It will begin with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. The tutorial will continue with the UVM register package, including how to create and manage stimulus and checking at the register level. The morning session will conclude with a review of all of the topics, showing how they fit together in a complex SOC verification environment.

Introduction of these fundamental concepts will be followed by several real-life user experiences including lessons learned in preparing transition to UVM, architecting reusable testbenches, debug techniques and use of TLM 2.0 in real verification environments.

This tutorial will appeal to new SystemVerilog users taking their first steps into constrained random verification as well as to power users looking to take advantage of the most recent developments in UVM. Working knowledge of SystemVerilog (IEEE 1800) and familiarity with at least one simulator is assumed.

More information and register.

Thursday | March 1st | 8:30am - 12:00pm
Design & Verification of Platform-Based, Multi-Core SoCs

The era of platform-based SoCs has arrived.

In order to realize the benefits of platform-based SoCs, users must be able to develop, optimize, integrate and verify differentiating hardware blocks and the software that defines the final system. Time-to-market and quality are keys to success. Consumers demand polished products. Software development and validation must begin on day 1 to avoid costly schedule delays. Multi-core platforms, with extensible coherent memory, increase the SoC architectural design, integration, verification, and debug challenges. Full system verification and test must begin early in order to adequately test the full breadth and depth of system architecture and performance and deliver the quality that today's market demands.

In this tutorial, we will cover the process of defining an SoC system based on platform subsystem IP, the development and integration of hardware acceleration blocks, analyzing system performance criteria, verification of the SoC functionality, the development and validation of software using virtual prototyping and acceleration technology and verification from block to SoC to full system.

Please join Mentor Graphics, ARM & Calypto for this session.

More information and register.

Booth # 801

Tuesday, February 28th
3:30pm - 6:30pm

Wednesday, February 29th
4:30pm - 7:00pm

Mentor Graphics delivers the most comprehensive and unified advanced verification portfolio available: including Questa® for high performance simulation and debug, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, processor-based hardware verification and Veloce® for high-performance system verification. This portfolio combined with Mentor's ESL technologies allow design and verification at higher levels of abstraction. This comprehensive solution supports UVM and OVM.

Come check out our latest demos at booth # 801.

Tuesday, February 28th

Full Papers:

• Low-Power SoC Verification: IP Reuse and Hierarchical Composting Using UPF
• Keeping Up with Chip: the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient
• Experience with OVM and Mixed-Signal Verification of an Impedance Calibration Block for a DDR Interface

Poster Papers:

• The Missing Link: The Testbench to DUT Connection
• Blending Multiple Metrics from Multiple Verification Engines for Improved Productivity
• Keeping Score - Techniques for Scoreboard Design and Development
• Random Stability - Don't Leave it to Chance!

Wednesday, February 29th

Full Papers:

• Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM Environment
• Relieving the Parameterized Coverage Headache
• Systematically Achieving CDC Verification Closure Based on Coverage Models and Coverage Metrics
• e/eRM to SV/UVM - Mind the Gap, But Don't Miss the Train
• There's Something Wrong Between Sally Sequencer and Dirk Driver – Why UVM Sequencers and Drivers Need Some Relationship Counseling
• Better Living Through Better Class-Based SystemVerilog Debug

Poster Papers:

• Metrics in SoC Verification: Not Just for Coverage Anymore
• Verification of Clock Domain Crossing: Jitter and Meta-Stability Tolerance Using Emulation
• Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software Environment
• Supplementing Simulation of a Flash Memory Subsystem with Formal Verification
  
  

More information and register for these events: www.dvcon.org