Advanced Verification Technologies in the Real World
No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are solutions – tools, methodologies and process that deliver revolutionary results with evolutionary enhancements to existing flows. This tutorial will include the technical details that engineers need today, blended with real users giving examples, results and advice for how these technologies were deployed on their projects.
The target audience for this archived seminar is:
- Walk - content is of general interest, particularly to managers, but also engineers.
- Transforming Verification and Verification Management
- UVM and OVM Methodology Update & Verification IP
- Intelligent Testbench Automation and Coverage Closure
- Power Aware Verification and UPF Based Tips and Tricks
- CDC Verification of an Accelerated Processing Unit
- Processor-Based Verification and Questa Codelink
- Walking the Walk Wrap Up and Recommendations
This session leads-off where all successful verification projects begin: verification planning and management. This includes verification plan creation, real-time tracking of progress against the plan, and analyzing results and trends throughout the project.
This session is an an update of verification methodologies UVM and OVM, including the use of pre-verified verification IP and successful transitioning from legacy methodologies to these industry standards. We hear from John Gryba on Alcatel Lucent’s process for applying OVM.
To radically decrease your time to coverage closure, this session will show how to apply intelligent automation of testing while retaining your investment in standard UVM and OVM verification environments, with a discussion from Chandramouli Ganapathy from Atheros Communications Inc.
In this session we next study applying low power design techniques with UPF to augment an existing flow for RTL and netlist; focusing on power verification techniques from the testbench perspective with a discussion from Anand Moghe from Cypress Semiconductor.
This session will show how formal technology solutions ease the verification of critical elements of your designs such as Clock-Domain Crossings and CDC synchronization logic. Including a presentation from Priyank Parakh from AMD on their usage of CDC Verification.
As the system is assembled, acceleration and emulation may be required for design size and performance. Additionally, the software also must be verified along with the hardware. Hear from Jerome Velardi on how ST Ericsson applied the co-verification in this session.
This session will wrap up the tutorial with a discussion of proven techniques that can be used for full SoC verification.