Design & Verification in the SoC Era
The challenges of verification continue growing exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. Yet, the continuing growth in the size of verification teams and the amount of project time dedicated to verification indicate the need for greater advances in productivity.
As we enter the era of SoCs, verification complexity will be driven by increased design complexity of multiple cores running many applications to deliver on-demand content in consumer devices such as tablets and smartphones.
It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that deliver 10-100x advances in verification are required. As the impact of software in electronic systems grows, verification solutions must expand to enable co-verification with advanced verification technology. Comprehensive solutions and methodology will integrate these innovative tools and enable real-time progress tracking, trend analysis and increased automation and efficiency of the verification process.
The target audience for this archived seminar is:
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Walk - content is of general interest, particularly to managers, but also engineers.
The seminar keynote by Harry Foster and Track 2: Accelerating Coverage Closure recordings are now available to view in segments or as a single file HD download.
Seminar tracks 1 and 3 were not recorded and the slides .pdf are available below.
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Track 1: System & SoC Design and Verification
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1.1 - Multicore ESL Design and Virtual Prototyping
1.2 - Multicore ESL Verification Refinement to RTL
1.3 - Accelerating Functional Verification from ESL to UVM
Track 3: UVM/OVM Applications
- Trends, Predictions and Forecasts - Part 1
- Trends, Predictions and Forecasts - Part 2
- Trends, Predictions and Forecasts - Part 3
- Trends, Predictions and Forecasts - Part 4
- iTBA - Accelerating Time to Coverage Closure - Part 1
- iTBA - Accelerating Time to Coverage Closure - Part 2
- iTBA - Accelerating Time to Coverage Closure - Part 3
- Understanding Coverage Holes - Part 1
- Understanding Coverage Holes - Part 2
- Understanding Coverage Holes - Part 3
- Focusing, Automation and Accelerating Coverage Closure with a Plan - Part 1
- Focusing, Automation and Accelerating Coverage Closure with a Plan - Part 2
- Focusing, Automation and Accelerating Coverage Closure with a Plan - Part 3
Just as ASIC complexity drove the innovation and adoption of RTL synthesis, constrained-random testing, assertion-based verification and functional coverage, the SoC era is driving innovations in design and verification. What defines the requirements for the SoC era? What is the future of design and verification for SoCs?
This session continues with Functional Verification Trends.
This session continues with Effort and Results.
This session concludes with What's Changed in Design and Verification and Q&A.
Achieving coverage closure is one of the most important, yet difficult challenges faced by verification engineers. But with no shortage of tools and techniques, most teams have still struggled to finish verification on time, until recently. The emergence of Intelligent Testbench Automation ("iTBA") now enables verification teams to achieve their coverage goals 10X to 100X faster than before. This session introduces iTBA, and shows how this new breakthrough can help you realize an order of magnitude gain in verification productivity. It will also highlight a real-life example of a verification team that accelerated its own functional verification process with Intelligent Testbench Automation, and now verifies more functionality in even less time.
This session continues with Galen Blake from Altera.
This session concludes with Galen Blake from Altera and Q&A.
So you’ve defined your coverage model, written your verification plan, and run verification – but you aren’t achieving full coverage. Now what? You need to analyze the results to understand where the coverage holes are, and for each one, why it is there. A coverage hole may indicate that the design is incomplete or incorrect. Or it may mean that the test environment is insufficient. Or it may simply mean that some IP block functionality is not used in this context. And there may be holes in your coverage model and verification plan that you cannot even see, because you failed to consider something. This session will review the analysis of coverage results to identify and respond to coverage holes appropriately. Along the way we’ll show how static analysis tools such as Questa CDC and Questa Formal can be used to help identify and address coverage holes.
This sessions continues with Coverage Model Holes.
This session continues with Coverage Model Holes and concludes with Coverage and Completeness and Q&A.
When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins or problems in the field soar. What’s required is an environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project and the ability to guide the process by a plan. Verification is a dynamic process with the design specification, design implementation and the verification plan changing over the duration of the project. It can take a lot of effort to keep things in sync and ensure that documents do not get stale or, worse still, features and testing fall between the cracks. Coverage models are used as metrics to measure if a feature has or has not been tested. To be able to track what has been verified it is necessary to have electronic closure between the verification plan and the coverage measurement to allow these to be kept in sync. Further links are required between the design implementation, design specification and the verification plan to ensure that all these are also kept in sync. Any changes to one should be immediately visible, ensuring that the verification process is kept on track and focused on the plan. This sessions will show how to apply Verification Planning techniques in process, tools and data management with Questa Verification Management and ReqTracer tools in order to accelerate their coverage closure and efficiently keep their plan in sync with changing requirements.
This session continues with Verification Plan Capture.
This session concludes with Tracking Coverage with a Plan and Q&A.