Verification Academy

Harry Foster

Harry Foster is Chief Verification Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored five books on verification--including the 2008 Springer book Creating Assertion-Based IP. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Modules: Evolving Verification Capabilities | Assertion-Based Verification | Clock-Domain Crossing Verification

Tom Fitzpatrick

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcommittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Module: Advanced UVM | Advanced OVM (& UVM - Universal Verification Methodology)

Rich Edelman

Rich Edelman is a Verification Methodologist specializing in helping customers adopt and deploy the UVM and OVM. Rich has worked in ASIC companies, EDA consulting, EDA start-ups, and 2 of the big three. Rich first got involved with the AVM while developing his “RPS training class”, which was an easy way for people to learn about the AVM. Rich’s verification interests range from DPI and transaction recording to register modeling, sequences and class-based debug. Rich has published many related conference papers, including a Best Paper on SystemVerilog DPI at DVCON, and various transaction recording papers with IPSOC. Rich received a BSEE, a BSCS and an MSCS from Washington University in St. Louis..

Module: UVM Express

Mark Peryer

Mark Peryer is a Verification Methodologist within the Design Verification and Technology division at Mentor Graphics and is responsible for developing and deploying verification methodologies and solutions. He developed his first verification environment for a graphics processor in the mid-eighties and although the languages and the techniques have changed, he has continued to work on hairy verification problems ever since. Mark is the author of many conference papers, articles and training classes and holds an honours degree in Electronic Engineering from Southampton University.

UVM/OVM Cookbook Contributing Author; Sequences, Testbench architecture and build, Registers.

Mike Horn

Michael Horn is a Principal Verification Architect specializing in helping ASIC and FPGA groups and companies to deploy UVM and OVM. He started his career in the telecom and storage industries doing design and verification. For the past several years, Michael has been working with Mentor Graphics to help Mentor's customers to use Mentor's tools, but also to grow the customers verification capabilities and techniques. He has been using high level verification languages since 1999 starting with Specman E then moving to Vera and now SystemVerilog. Michael has co-authored numerous publications and conference papers including papers for DVCon. He received his BSEE from the University of Illinois at Urbana-Champaign.

UVM/OVM Cookbook Contributing Author

Dr. Hans van der Schoot

Dr. Hans van der Schoot is a recognized specialist in verification technology, and employed as a methodologist in the Emulation Division at Mentor Graphics. Hans has a solid background and wealth of knowledge in functional verification from his many years as a researcher, engineer and consultant in the field, with extensive practical experience providing verification methodology and implementation consulting and training services in the industry. He has authored multiple papers pertinent to hardware verification and software testing. Hans obtained his doctorate degree in computer science from the University of Ottawa, Canada, after graduating from the University of Twente in the Netherlands, also in computer science. Prior to joining Mentor Graphics, he was the Vice President Engineering at XtremeEDA. He has also worked independently as an expert design verification consultant, following senior engineering positions with Qualis Design, PMC-Sierra, and Nortel Networks.

Module: Acceleration of SystemVerilog Testbenches with Co-Emulation

Peet James

Peet James was recently described by a customer as a “Verification Animal”. Over his 25+ years of experience he has always had one foot entrenched in improving both design and verification methodologies and processes, and the other foot entrenched in directly applying these to actual projects. Peet’s specialty is verification planning and management where he typically takes a team of engineers and guides them into architecting, documenting and implementing successful verification environments. Peet started out working at Sperry, IBM & Motorola, and then moved into consulting as one of the principles at Qualis Design Corporation. Peet has been with Mentor Graphics for the past 3 years. Peet has many award winning papers and is a published author of a book on verification planning.

Module: Verification Planning and Management Introduction

Ray Salemi

Ray Salemi is a 20-year veteran of the EDA industry and is an expert in the use of RTL in design flows. He is the author of "FPGA Simulation: A Complete Step-by-Step Guide" and of "Leading After a Layoff: Reignite Your Team's Productivity Quickly" Ray stared in EDA as the manager of customer support for Gateway Design Automation -- the founder of Verilog and then for Cadence Design Systems. As a CAE Manager for Sun Microsystems, Ray led teams that created Sun's ASIC development environments. Recently Ray has worked for Exemplar, and Mentor Graphics focusing on FPGA design, verification, and synthesis.

Module: Evolving FPGA Verification Capabilities

Mark Olen

Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.

Module: Intelligent Testbench Automation

Steve Chappell

Steve Chappell is a Solutions Architect specializing in Intelligent Testbench Automation and other advanced verification techniques. He has been designing and verifying (or helping others design and verify) hardware and software products in the Semiconductor IP and EDA industries for about fifteen years, the last five with Mentor Graphics. He has been a regular presenter and track chair at User2User Conferences across the country. He holds BSEE and MSEE degrees, both from Stanford University..

Module: Intelligent Testbench Automation

John Stickley

John Stickley is a Verification Technologist at Mentor Graphics Emulation Division. His research interests are in electronic design verification methodologies. His most recent work at Mentor Graphics has been in the area of high-performance emulation based verification techniques in particular with using SystemVerilog OVM/UVM and SystemC TLM-2.0 based testbench modeling - particularly in conjunction with the use of virtual processor platforms. He has 30 years of experience in the EDA industry and holds a BSEE degree from Cornell University.

Module: Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation

John Aynsley

John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in simulation, languages (particularly VHDL, SystemVerilog, and SystemC), hardware verification and system modeling, and has written many training courses and technical papers in these areas. He is co-author of the IEEE 1666 SystemC standard, author of the OSCI TLM-2.0 LRM, and an active contributor to several technical working groups and forums. His current role spans technical consulting, technical marketing, and business management.

Modules: Basic OVM (Open Verification Methodology) | Basic UVM (Universal Verification Methodology)

Chuck Seeley

Chuck Seeley has over 27 years of experience in engineering design and verification, and technical marketing. As a Technical Marketing Engineer at Mentor Graphics Corporation he specializes in both assertion-based verification and coverage driven verification methods. He holds a BSEE from Portland State University.

Session: Questa Simulation ABV Demo

Mark Eslinger

Mark Eslinger has over 20 years of experience in chip design and verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics, Mr. Eslinger has a special focus on assertion-based methods and formal verification. He works with customers worldwide to help them adopt advanced methodologies. Prior to Mentor Mr. Eslinger held positions in the engineering and technical marketing organizations in the semiconductor, systems, and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. He holds a MSEE from Santa Clara University.

Session: Questa Formal Verification Demo

Kurt Takara

Kurt Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.

Session: Questa CDC Verification Demo