Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
What could be the reason for infinite loop in our code when dealing with sequence and driver	1	47	April 24, 2024
Register mirrored value should update until an event happens in temporal domain	1	36	April 25, 2024
Whether to use TLM ports or class object set in the uvm_config_db	4	53	April 24, 2024
Hierarchical uvm_reg_block add hdl path	0	40	April 24, 2024
Basic rule to use assertion in UVM assertion	1	64	April 23, 2024
Uvm_hdl_read using macro for string path	1	33	April 22, 2024
If virtual sequencer contain a source sequencer and and destination sequencer and in test I am calling seq.start(envh.v_seqrh) then how ill the tool know to start the sequences on source sequencer or destination sequencer	2	49	April 22, 2024
Using uvm_config_db to register binded interfaces UVM	4	66	April 21, 2024
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM , uvm_reg_bit_bash	4	1940	April 19, 2024
How to create array of agent in environment with UVMF yaml UVMF	1	114	April 19, 2024
A better way of getting response back to a waiting sequence?	2	74	April 18, 2024
** Error: /vobs/ss_restart_vseq.sv(714): 'pass_ssr_vseq' is not a task name UVM	3	49	April 18, 2024
How to manage compare policies if uvm_comparer should be avoided? compare , uvm_comparer , do_compare	0	47	April 17, 2024
Driver sequencer communication in uvm	4	88	April 16, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique SystemVerilog , UVM , uvm_reg , RAL-UVM	1	996	April 16, 2024
Override by sequence type changes handle type everywhere whereever it is declared in driver even if it is parameterized or how?	2	48	April 16, 2024
Backdoor access to a reg inside an unnamed primitive	4	113	April 15, 2024
Scoreboard sampling	2	85	April 14, 2024
How to use a variable in uvm test and same variable in the sequence	2	82	April 12, 2024
Function New Constructor SystemVerilog , UVM	1	78	April 11, 2024
Null object reference - Mod 12 Counter design Verification	2	62	April 11, 2024
Configuring Sequences \| UVM Cookbook - question on example code uvm_config_db	1	66	April 10, 2024
Interview Question on UVM	4	123	April 8, 2024
UVM RAL Register Name Access UVM	4	68	April 8, 2024
DUT reference model location? SystemVerilog , UVM	2	81	April 7, 2024
UVM Agent without a sequencer	1	71	April 7, 2024
UVM RAL \| Errors in REG & RAL FILES UVM	1	70	April 6, 2024
Best Practice for Unit Tests Extending Chip-Level Tests SystemVerilog , Inheritance	1	72	April 6, 2024
Memory usage keeps increasing as test runs UVM	5	91	April 4, 2024
UVM severity override from UVM_INFO to UVM_ERROR and UVM_VERBOSITY == UVM_NONE	2	67	April 4, 2024