Topics tagged sequence

Topic	Replies	Views	Activity
Sequence task get stuck in wait_for_grant() UVM UVM , sequence , wait_for_grant	7	337	December 14, 2023
Assertion SystemVerilog SystemVerilog , assertion , Package , sequence , systemverilogassertionSVA	2	237	November 17, 2023
Sequence Library UVM UVM , sequence , sequence-library , configurability	3	319	September 8, 2023
Sequence not getting config object from config_db UVM UVM , sequence , uvm-register-sequences , uvm-config_db	7	404	July 19, 2023
Can we start one sequence onto the driver while it is driving another sequence? UVM UVM , sequence , UVM-monitor-sequencer-Agent-TLM_FIFO , UVM-sequence-sequencer-nested_sequence-transaction	2	316	June 9, 2023
Can I send parent sequence item and child sequence item at the same time to the Driver? UVM UVM , sequence	1	457	May 11, 2023
How to mask the write data and read data in a register in UVM sequence UVM UVM , registers , sequence , access-register-in-uvm-monitor , registers_testing , register-masking	1	440	February 21, 2023
Error on sequencer - send_request failed to cast sequence item UVM UVM , sequence , casting , uvm_fatal	9	2436	February 1, 2023
Issue when using uvm_reg update method: "Accessing non-static members of a null object is not allowed" UVM UVM , sequence , uvm_reg	2	625	January 26, 2023
Systemverilog inheritance question SystemVerilog SystemVerilog , sequence , Inheritance	4	479	January 24, 2023
How can one write a UVM sequence for cache eviction? Lets suppose main memory is 4GB. 64KB Cache, 4 way associative, 64B cache line. Any ideas would be appreciated UVM SystemVerilog , UVM , sequence , delay-uvm_components	0	366	January 14, 2023
What is the use of sequence overrides UVM UVM , override , sequence , set_type_override , uvm_set_inst_override	0	452	August 29, 2022
How sequences is start? UVM UVM , sequence , uvm-sequence-test	1	476	June 26, 2022
Uvm sequence for registers test UVM UVM , sequence , regmodel	2	611	June 20, 2022
UVM Constrains inside a sequence are ignored UVM UVM , sequence , constraint-randomization , sequence-item , systemverilog-uvm	5	756	June 13, 2022
SVA Sequence Subtleties (Sequence fusion / Sequence concatenation) SystemVerilog SystemVerilog , assertion , sequence , verifcation , Assertion-property	4	595	May 25, 2022
I don't understand these sentences about concurrent assertion and simulation event SystemVerilog SystemVerilog , assertion , sequence , scheduling	3	513	April 27, 2022
Reactive agent for memory storage UVM UVM , sequence , reactive-agent	11	3227	March 18, 2022
Get_response function in sequence does not get unblocked after put_response UVM UVM , sequence , get_response , driver , systemverilog-uvm	2	783	February 3, 2022
Passing queue through sequence_item UVM UVM , sequencer , sequence , driver , Queues , sequence-item	2	1000	January 22, 2022
SEQUENCE ITEM UVM UVM , sequence	1	540	December 6, 2021
Multiple packet in sequence and how to send those packet to specific seqr? UVM UVM , sequence	0	716	October 22, 2021
Sequence in go-to reptition and non-consecutive repetition SystemVerilog SystemVerilog , SVA , sequence	1	596	October 20, 2021
Address generation for use in sequences UVM UVM , sequence , address-generation	0	527	October 13, 2021
Default sequence in UVM UVM UVM , default_sequence , sequence	3	6420	October 13, 2021
Simulation changing with respect to Sequence name UVM UVM , sequence , create	3	650	August 26, 2021
Sequence to that respond to done signal UVM UVM , sequence , get_response , Response-API , sequence-body	14	1589	August 23, 2021
Access a queue in base_test from a sequence UVM UVM , sequencer , uvm-uvm_config_db , sequence , base_test-uvm_tlm_fifo	7	1132	August 18, 2021
P_sequencer is null_object in sequence's new function UVM UVM , p_sequencer , sequence , Null-Object-Access	1	784	July 5, 2021
UVM objection raising mechanism UVM UVM , sequence , Related-to-UVM-phases , UVM-OBJECTIONS	7	1546	June 8, 2021