Topics tagged systemverilog

Topic	Replies	Views	Activity
Smart way to bundle up multiple RTL signals when passing to monitor SystemVerilog SystemVerilog , UVM-monitor	1	18	May 2, 2024
Discrepancy on legality of the consequent SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA , SVA-Assertion	6	47	May 1, 2024
Randc variable randomization inside top sequence class SystemVerilog SystemVerilog , constraint-randomization , randomization , randc-usage-constraint , systemverilog-constraint	3	19	May 1, 2024
How to cover unsigned int UVM SystemVerilog , UVM , Coverage	1	33	April 30, 2024
SystemVerilog Hiearchial Reference to UUT Internal Signal? SystemVerilog SystemVerilog	2	22	April 30, 2024
System verilog inheritance for sequences SystemVerilog SystemVerilog	4	28	April 30, 2024
Using sequence method triggered within Sampled value functions SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	5	69	April 27, 2024
How can you set order for the execution of initial begin blocks without using event or wait statements? SystemVerilog SystemVerilog	1	24	April 27, 2024
How text macro affect inside and outside pkg? SystemVerilog SystemVerilog , compilation-macro	2	21	April 27, 2024
Performance problem SystemVerilog SystemVerilog	3	55	April 24, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	17	4284	April 24, 2024
Vopt-13412) Virtual methods of an object or built-in method are not allowed in event control expressions SystemVerilog SystemVerilog	1	28	April 23, 2024
Arr.sum() - constraint SystemVerilog SystemVerilog , systemverilog-constraint	1	54	April 23, 2024
What is the general difference between static and dynamic events in SystemVerilog? SystemVerilog SystemVerilog	3	912	April 23, 2024
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	595	April 23, 2024
How to pass delay through a variable in assertion SystemVerilog SystemVerilog	7	2012	April 23, 2024
Empty bin warning for disabled cover point Coverage SystemVerilog , Coverage	1	34	April 19, 2024
Elaboration time constant for enumerated type.num() SystemVerilog SystemVerilog	2	34	April 18, 2024
Parameter type in interface SystemVerilog SystemVerilog , interface	1	41	April 16, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	981	April 16, 2024
Illegal range in part select SystemVerilog SystemVerilog	10	4769	April 16, 2024
APB state operation SystemVerilog SystemVerilog	0	32	April 15, 2024
NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED SystemVerilog SystemVerilog , virtual-interface-scoreboard-uvm	5	359	April 15, 2024
Constraint array SystemVerilog SystemVerilog , systemverilog-constraint	2	92	April 12, 2024
Function New Constructor UVM SystemVerilog , UVM	1	56	April 11, 2024
How do I avoid using #0 in an interface monitor SystemVerilog SystemVerilog , UVM	3	69	April 10, 2024
How the within syntax is working in SVA SystemVerilog SystemVerilog , assertion , SVA	7	2186	April 10, 2024
System Verilog Fine grain Process SystemVerilog SystemVerilog	2	69	April 9, 2024
Backdor access without using RAL model SystemVerilog SystemVerilog	3	67	April 8, 2024
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	6304	April 7, 2024