Osmosis 2022

Osmosis 2022 Header

Osmosis 2022 Overview

Osmosis 2022 Presentations

1. Presentations

   • The state of functional verification: Crisis or opportunity?

     Formal Verification Dec 08, 2022 Harry Foster mp4

   • Make formal simple and easy-to-use with generated Assertion IP

     Formal Verification Dec 08, 2022 Tobias Ludwig - Lubis Eda mp4

   • The X-factors of X-checking

     Formal Verification Dec 08, 2022 Kanthi Palaniappan mp4

   • Formal coverage: an approach to analyze property holes

     Formal Verification Dec 08, 2022 Aishwarya Sridhar mp4

   • How formal lights up your RISC-V verification avenue

     Formal Verification Dec 08, 2022 Philippe Luc mp4

   • Accelerator quick error detection: Verification of hardware accelerators

     Formal Verification Dec 08, 2022 Saranyu Chattopadhyay mp4

   • Exhaustive trust & security verification by leveraging emerging standards

     Formal Verification Dec 08, 2021 John Hallman mp4

   • Crossing the RISC-V customization barrier with formal

     Formal Verification Dec 08, 2022 Pascal Gouedo mp4

   • A novel approach to formal FW/HW co-verification

     Formal Verification Dec 08, 2022 Djones Lettnin mp4

   • UPEC: Side channel detection with formal verification

     Formal Verification Dec 08, 2022 Keerthi Devraj mp4

   • EC-FPGA updates with an introduction to instance mapping

     Formal Verification Dec 08, 2022 Kevin Urish mp4

Osmosis 2022 Interviews

1. Osmosis Presenter Interviews

   • Harry Foster - Siemens EDA

     Formal Verification Dec 08, 2022 Harry Foster mp4
     Interview with Harry Foster of Siemens EDA about the surprising results from the 2022 Wilson Research Study and Osmosis' presentations.

   • Holger Busch - Infineon

     Formal Verification Dec 08, 2022 Holger Busch - Infineon mp4
     Interview with Holger Busch of Infineon about the origins of formal and how the presentations at Osmosis show how far formal verification has come.

   • Katharina Ceesay-Seitz - ETH Zurich

     Formal Verification Dec 08, 2022 Katharina Ceesay-Seitz mp4
     Interview with Katharina Ceesay-Seitz of ETH Zurich about the value of attending Osmosis.

   • Philippe Luc - Codasip

     Formal Verification Dec 08, 2022 Philippe Luc mp4
     Interview with Philippe Luc of Codasip about his presentation on How formal lights up your RISC-V verification avenue.

   • Saranyu Chattopadhyay - Stanford University

     Formal Verification Dec 08, 2022 Saranyu Chattopadhyay mp4
     Interview with Saranyu Chattopadhyay of Stanford University about his presentation on Accelerator quick error detection: Verification of hardware accelerators.